VLSI SPECSInterface
13 source-linked records from 4 published manufacturer or standards contexts. Values remain product- and condition-specific.
UCIe 2.0
Interface entity connected to packages, chiplets and public standards metadata.
UCIe ConsortiumAs of 2026-08-2602UCIe 3.0
Version record for public release metadata and mode-conditioned comparisons.
UCIe ConsortiumAs of 2026-08-2603UCIe 1.1
Backward-compatible UCIe revision record.
UCIe ConsortiumAs of 2026-08-2604CXL 4.0
Publicly announced CXL revision; retain version, release date and access conditions only.
CXL ConsortiumAs of 2026-08-2605CXL 3.2
Version-level record for a released CXL specification.
CXL ConsortiumAs of 2026-08-2606CXL 3.1
Source-linked revision entity for fabric and memory-system research.
CXL ConsortiumAs of 2026-08-2607CXL 3.0
Source-linked CXL revision with public high-level protocol taxonomy.
CXL ConsortiumAs of 2026-08-2608PCI Express 7.0
Public release metadata for the PCIe 7.0 base specification.
PCI-SIGAs of 2026-08-2809PCI Express 6.x
Revision-family record; electrical and protocol details remain version-specific.
PCI-SIGAs of 2026-08-2810USB4 Version 2.0
Public USB4 revision metadata without reproducing controlled specification text.
USB-IFAs of 2026-08-2811UCIe 1.0
First released UCIe generation represented at version-metadata level.
UCIe ConsortiumAs of 2026-08-2812CXL 2.0
Released CXL revision with only public high-level feature metadata.
CXL ConsortiumAs of 2026-08-2813CXL 1.1
Historical CXL revision retained for compatibility and genealogy research.
CXL ConsortiumAs of 2026-08-28Comparison rule
Marketing node names, nominal rates and package labels are not treated as equivalent unless the underlying public definitions and conditions match.