VLSI SPECSSpecification graphVLSI KOREA

SOURCE-LINKED SEMICONDUCTOR SPECIFICATION GRAPH

Compare the condition.
Not just the number.

칩·메모리·공정·패키지·인터페이스의 단위, 조건, 기준일과 출처를 한 화면에서 맞춰 봅니다.

Published
45
Domains
8
Roadmaps
5
OPEN DATA PORT Free · no sign-in · source-linked fields
CSV ↓JSON ↗
LIVE COMPARISON / PUBLIC EVIDENCE2026-08-28
FIELDHBM4SPHBM4
GenerationHBM4JEDEC technology focusNot publishedNo evidence
Product metricsSupplier-specificDo not normalize without conditionsNot publishedNo evidence
Standard documentVerify version before displayJEDEC document searchNot publishedNo evidence
NameNot publishedNo evidenceSPHBM4JEDEC homepage release title
PositioningNot publishedNo evidenceHBM4-class bandwidth on organic substratesJEDEC release title

Different definitions remain separate. Missing public values never become zero.

01 / ENGINEERING LAYERS

Move through the stack.

각 레이어는 같은 필드 체계가 아니라, 해당 기술에 맞는 조건과 근거 체계를 가집니다.

01Interface13records ↗02Manufacturing12records ↗03Standard9records ↗04Packaging6records ↗05Memory5records ↗06Compute Architecture2records ↗07EDA Flow2records ↗08Architecture1records ↗
02 / ROADMAP STATES

Announced is not shipping.

미래 정보의 상태를 하나의 연도로 뭉개지 않고 발표, 확인, 샘플링, 양산, 출하로 분리합니다.

01

Foundry Process Roadmap

Announced, sampling, HVM and shipping states kept separate with claim-level sources.

AnnouncedConfirmedSamplingHVMShipping
02

Memory & HBM Roadmap

Generation and product milestones with public-source confidence and as-of dates.

AnnouncedSamplingQualifiedShippingSuperseded
03

Open chiplet-interconnect releases

Track UCIe release states without projecting adoption.

AnnouncedReleasedSuperseded
04

CXL specification releases

Track release announcements, not platform deployment forecasts.

AnnouncedReleasedSuperseded
05

Open PDK documentation releases

Track document/version changes with no fabrication-readiness inference.

ConfirmedUpdatedSuperseded
03 / PUBLISHED RECORDS

Open the evidence.

45 public records with source, date, scope and confidence on the detail page.

01 · Interface

UCIe 2.0

Interface entity connected to packages, chiplets and public standards metadata.

UCIe Consortium · 2026-08-26 ↗02 · Interface

UCIe 3.0

Version record for public release metadata and mode-conditioned comparisons.

UCIe Consortium · 2026-08-26 ↗03 · Interface

UCIe 1.1

Backward-compatible UCIe revision record.

UCIe Consortium · 2026-08-26 ↗04 · Interface

CXL 4.0

Publicly announced CXL revision; retain version, release date and access conditions only.

CXL Consortium · 2026-08-26 ↗05 · Interface

CXL 3.2

Version-level record for a released CXL specification.

CXL Consortium · 2026-08-26 ↗06 · Interface

CXL 3.1

Source-linked revision entity for fabric and memory-system research.

CXL Consortium · 2026-08-26 ↗07 · Interface

CXL 3.0

Source-linked CXL revision with public high-level protocol taxonomy.

CXL Consortium · 2026-08-26 ↗08 · Memory

HBM4

Standards-taxonomy entity; capacities and bandwidth remain product-specific.

JEDEC members · 2026-08-26 ↗09 · Memory

SPHBM4

JEDEC-named HBM4-class bandwidth standard entity; preserve product and topology conditions.

JEDEC members · 2026-08-26 ↗10 · Compute Architecture

RISC-V RVA23

Profile entity with status and implementation scope separated.

RISC-V International · 2026-08-26 ↗11 · Compute Architecture

RISC-V Vector Extension

Open ISA extension entity with version-specific source links.

RISC-V International · 2026-08-26 ↗12 · EDA Flow

OpenLane 2

Open-source ASIC-flow entity for reproducible toolchain navigation.

OpenLane · 2026-08-26 ↗
Search every recordBuild another comparison