VLSI SPECSCXL 3.0 vs UCIe 2.0
같은 이름의 공개 필드를 맞춰 비교합니다. 서로 다른 정의·조건이나 공개되지 않은 값은 동일하다고 추정하지 않습니다.
| Field | CXL 3.0 | UCIe 2.0 | Evidence note |
|---|---|---|---|
| Category | Interface | Interface | Taxonomy labels; not equivalence proof |
| Revision | 3.0 | Not published | Official specification / No right evidence |
| Maximum data rate | 64 GT/s | Not published | Official public specification / No right evidence |
| Protocols | CXL.io / CXL.cache / CXL.mem | Not published | Official public specification / No right evidence |
| Version | Not published | 2.0 | No left evidence / Official metadata required |
| Bandwidth | Not published | Mode-specific | No left evidence / Official specification required |
| Related | Not published | CXL · PCIe · Chiplets | No left evidence / Graph relationship |
Source pages: Compute Express Link Consortium ↗ · UCIe Consortium specifications ↗