VLSI SPECSOpenLane 2 vs UCIe 2.0
같은 이름의 공개 필드를 맞춰 비교합니다. 서로 다른 정의·조건이나 공개되지 않은 값은 동일하다고 추정하지 않습니다.
| Field | OpenLane 2 | UCIe 2.0 | Evidence note |
|---|---|---|---|
| Category | EDA Flow | Interface | Taxonomy labels; not equivalence proof |
| Project | OpenLane 2 | Not published | Official docs / No right evidence |
| Flow scope | RTL-to-GDSII flow | Not published | Official docs / No right evidence |
| PDK support | Version-dependent | Not published | Verify release notes / No right evidence |
| Version | Not published | 2.0 | No left evidence / Official metadata required |
| Bandwidth | Not published | Mode-specific | No left evidence / Official specification required |
| Related | Not published | CXL · PCIe · Chiplets | No left evidence / Graph relationship |
Source pages: OpenLane project ↗ · UCIe Consortium specifications ↗